Optimization Algorithms for Reconfigurable Fpga Based Architectures: Fpga, Design Flow, Reconfigurable Architectures, System on Programmable Chip

Dynamically reconfigurable architectures (DRA) have the potential for achieving high performance at a relatively low cost for a wide range of applications. DRA combine programmable processing units with reconfigurable hardware units. The later is usually based on dynamically reconfigurable Field Programmable Gate Array (FPGA). Designers have used the temporal partitioning approach to divide the application into temporal partitions, which are configured one after the one on target FPGA. The first partition receives input data, performs computations and stores the intermediate data into an on-board memory. The device is then reconfigured for the next partition, which computes results based on intermediate data from the previous partition. A controller interacts with both the reconfigurable hardware and the memory and is used to load new configuration. The temporal partitioning has become an essential issue for several important VLSI applications. Application with several tasks has entailed problem complexities that are unmanageable for existing programmable device.