Analysis and Design of a Dram Cell for Low Leakage: Process Level Techniques for Leakage Reduction

In Dynamic Random Access Memory, every cell experiences leakage current which consumes part of the stored charge. As the DRAM cell size is shrinking, the leakage is increasing. To maintain the desired data retention time, the leakage current must be kept within the acceptable limit. So, leakage reduction in memories is a topic of great challenge and interest in researchers. This book presents the analysis and design of a DRAM cell for low leakage. For the analysis, trench capacitor DRAM cell has been considered. For the design of trench capacitor DRAM cell, 0.18 ?m submicron nMOSFET as access transistor and the conventional trench capacitor as storage device have been considered. Various DRAM cell structures, leakage mechanisms in a DRAM cell and process-level techniques for leakage reduction have been reviewed. Process simulation and device simulation of DRAM cell have been done using the ATHENA/ATLAS packages of SILVACO. This book will help the beginners as the book reviews the previous work done by many researchers and provides the trends in DRAM cell designs, theoretical knowledge of leakage mechanisms in DRAM cell and process/device simulation of DRAM cell.